1. Field of Invention
The present invention is related to magnetic random access memory and in particular to reference averaging to enhance the read out margin.
2. Description of Related Art
Information is stored in a magnetic random access memory (MRAM) in the form of parallel and anti-parallel magnetic states of a magnetic tunnel junction (MTJ). The resistance of the parallel state is lower than that of the anti-parallel state. Data is stored in an MTJ by whether the state of the magnetic material of the MTJ is parallel or anti-parallel. Read out of the data in a sense amplifier is current flow from the MTJ compared to a reference that is positioned midway between current flow from an MTJ that has a magnetic parallel state and one that is anti-parallel.
To reduce readout variation and to produce a better fit with the threshold for deciding the state of an MTJ, a constant reference voltage or a constant reference current have been tried, but constant voltage and constant current references usually can not track temperature and process variations of the MTJ cells. These constant references cannot track the parasitic resistance and capacitance in the signal paths. Therefore, constant voltage and current references are not suitable for high speed operation. Self reference scheme have been considered, but it usually requires a cell to be read twice at different time intervals, which causes a longer time interval, charge loss, and possible influence of disturbance.
U.S. Pat. No. 7,239,537 B2 (DeBrosse et al.) is directed to a calibrated magnetic random access memory current sense amplifier, wherein a plurality of trim transistors that are individually activated to compensate for device mismatch relative to the data and sense sides of a sense amplifier. In U.S. Pat. No. 7,167,389 B2 (Iwata.) a magnetic random access memory is directed to a use of reference cells to help facilitate read and write operations. U.S. Pat. No. 7,038,959 B2 (Garni) is directed to a sense amplifier and a method for sensing an MRAM cell, comprising data cells, reference cells and dummy cells. U.S. Pat. No. 6,822,895 B2 (Yamada) is directed to a reference bit line connected in common for a plurality of bit lines, wherein a sense amplifier connected to a bit line and the reference bit line. U.S. Pat. No. 6,700,814 B1 (Nahas et al.) is directed to the use of a mock MRAM array and a mock sense amplifier, wherein a control circuit maintains current through cells of the mock MRAM at a value proportional to a reference current through variations in average bit cell resistance.
An article by Thomas W. Andre, Joseph J Nahas, Chita K. Subramanian, Bradley J Garni, Halbert S. Lin, Asim Omar and William L. Martino, Jr. titled “A 4 Mb 0.18 um 1T1MTJ Toggle MRAM With Balanced Three Input Sensing Scheme And Locally Mirrored Unidirectional Write Drivers”, IEEEE Journal of Solid State Circuits, vol. 40, pp. 301-309, January 2005, is directed a five level CMOS technology with a single toggling magneto tunnel junction to achieve a small chip size using unidirectional programming currents controlled by mirrored write drivers and a balanced three input current mirror sense amplifier for a read operation. An article by Gitae Jeong, Wootoung Cho, Sujin Ahn, Hongsik Jeong, Gwanhyeob Koh, Youngnam Hwang and Kinam Kim, titled “A 0.24 um 2.0 V 1t1MTJ 16 Kb Nonvolatile Magnetoresistance RAM With Self Reference Sensing Scheme”, IEEE Journal of Solid State Circuits, vol. 38, pp. 1906-1910, November 2003, is directed to a one transistor and one magnetic-tunnel-junction magneto resistance RAM using a self reference sensing scheme for reliable sensing margin.